A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems. In particular, flash memory is a type of electronic memory media that can be rewritten and retain content without consumption of power. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors. Flash memory technology can include NOR flash and/or NAND flash, for example. NOR flash evolved from electrically erasable read only memory (EEPROM) chip technology, in which, unlike flash, a single byte can be erased; and NAND flash evolved from DRAM technology. Flash memory devices can be less expensive and denser as compared to many other memory devices, meaning that flash memory devices can store more data per unit area.
Flash memory has become popular, at least in part, because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be used in many portable electronic products, such as cellular phones, computers, voice recorders, thumbnail drives, and the like, as well as in many larger electronic systems, such as automobiles, airplanes, industrial control systems, etc. The fact that flash memory can be rewritten as well as its retention of data without a power source, small size and light weight have all combined to make flash memory devices a useful and popular means for transporting and maintaining data.
Flash memory typically comprises an array of nonvolatile memory cells wherein data (e.g., one or more bits of data) can be stored. One type of flash memory comprises multi-level memory cells (e.g., quad-level memory cells) where each level can be associated with a respective data state. The multi-level memory cells also can comprise more than one memory element in which data can be stored. For example, a quad-level flash memory cell can comprise two memory elements that each can be programmed to four levels resulting in a memory cell that can have sixteen available data states and can store four bits of data. Each level of a multi-level memory cell can have a respective region or window that is associated with a respective data state.
For example, in a quad-level memory cell, there can be a first level that can be an erase state, where a memory element that has a charge level stored therein that is less than a predetermined threshold voltage level corresponding to the end of the window for the first level can be in an erase state. A second level can be associated with a first program level (e.g., first program state), where the window for the first program level can be defined by an upper and a lower threshold voltage levels, where the lower threshold voltage level can be adjacent to the threshold voltage level corresponding to the upper bound of the window associated with the first level and the upper threshold voltage level can define the upper bound of the second level. A memory element with a charge level that falls between the upper and lower threshold levels for the window for the first program level can be programmed to the first program state (e.g., data level 2). A third data level can be associated with a second program level (e.g. second program state), where the window for the second program level can be defined by an upper and a lower threshold voltage levels, where the lower threshold voltage level can be adjacent to the threshold voltage level corresponding to the upper bound of the window associated with the second level and the upper threshold voltage level can define the upper bound of the third level. A memory element with a charge level that falls between the upper and lower threshold levels for the window for the second program level can be programmed to the second program state (e.g., data level 3). A fourth level can be associated with a third program level (e.g., third program state), where the window for the third program level can be defined by a lower threshold voltage level that can be adjacent to the threshold voltage level corresponding to the upper bound of the window associated with the third level. A memory element with a charge level that is higher than the lower threshold voltage level for the window for the third program level can be programmed to the third program state (e.g., data level 4).
Over time, as the memory is subject to erase cycles and/or other use that can cause wear to the memory, the read margins for each level can become smaller (e.g., the windows for each level can become smaller), which can result in data retention loss and/or read errors with regard to stored data. To facilitate improved programming of multi-level memory cells and reduction of data retention loss with regard to memory cells, it is desirable to employ programming techniques that can result in very tight threshold voltage distribution widths for each level of a multi-level memory cell.